View LTC1544_1115076.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 LTC1544 software-selectable multiprotocol transceiver d2 d1 LTC1544 rts dtr dsr dcd cts d3 r2 r1 r4 r3 d2 ltc1543 ll txd scte txc rxc rxd 2 14 24 11 15 12 17 9 3 1 4 19 20 623 22 5 13 8 10 18 7 16 1544 ta01 ltc1344a d3 r2 r1 r3 d1 txd a (103) txd b scte a (113) scte b rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b ll a (141) sg (102) shield (101) db-25 connector txc a (114) txc b dcd a (107) dcd b dsr a (109) dsr b d4 dte or dce multiprotocol serial interface with db-25 connector , ltc and lt are registered trademarks of linear technology corporation. n data networking n csu and dsu n data routers n software-selectable transceiver supports: rs232, rs449, eia530, eia530-a, v.35, v.36, x.21 n tuv/detecon inc. certified net1 and net2 compliant (test report no. net2/102201/97) n tbr2 compliant (test report no. ctr2/022701/98) n software-selectable cable termination using the ltc1344a n complete dte or dce port with ltc1543, ltc1344a or ltc1546 with integrated termination n operates from single 5v supply with ltc1543 the ltc ? 1544 is a 4-driver/4-receiver multiprotocol trans- ceiver. the LTC1544 and ltc1543 form the core of a complete software-selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 or x.21 protocols. cable termination for the ltc1543 may be implemented using the ltc1344a software-selectable cable termination chip or by using existing discrete designs. the ltc1546 includes software-selectable cable termination on- chip. the LTC1544 runs from a 5v supply and the charge pump on the ltc1543 or ltc1546. the part is available in a 28-lead ssop surface mount package. features descriptio u applicatio s u typical applicatio u
2 LTC1544 order part number (note 1) supply voltage, v cc ................................................ 6.5v input voltage transmitters ........................... C 0.3v to (v cc + 0.3v) receivers ............................................... C 18v to 18v logic pins .............................. C 0.3v to (v cc + 0.3v) output voltage transmitters .................. (v ee C 0.3v) to (v dd + 0.3v) receivers ................................ C 0.3v to (v cc + 0.3v) v ee ........................................................ C 10v to 0.3v v dd ....................................................... C 0.3v to 10v short-circuit duration transmitter output ..................................... indefinite receiver output .......................................... indefinite v ee .................................................................. 30 sec operating temperature range LTC1544cg ............................................. 0 c to 70 c LTC1544ig ........................................ C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c LTC1544cg LTC1544ig t jmax = 150 c, q ja = 65 c/ w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc v dd d1 d2 d3 r1 r2 r3 d4 r4 m0 m1 m2 dce/dte v ee gnd d1 a d1 b d2 a d2 b d3/r1 a d3/r1 b r2 a r2 b r3 a r3 b d4/r4 a invert r1 d2 d1 r2 d3 g package 28-lead plastic ssop r3 d4 r4 consult factory for military grade parts. the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) symbol parameter conditions min typ max units supplies i cc v cc supply current (dce mode, rs530, rs530-a, x.21 modes, no load 2.7 ma all digital pins = gnd or v cc ) rs530, rs530-a, x.21 modes, full load l 95 120 ma v.28 mode, no load l 12 ma v.28 mode, full load l 12 ma no-cable mode l 10 200 m a i ee v ee supply current (dce mode, rs530, rs530-a, x.21 modes, no load 2.1 ma all digital pins = gnd or v cc ) rs530, x.21 modes, full load 14 ma v ee = C 5.6v (rs530, rs530-a modes) rs530-a, full load 25 ma v ee = C 8.46v (v.28 mode) v.28 mode, no load 1 ma v.28 mode, full load 12 ma no-cable mode 10 m a i dd v dd supply current (dce mode, rs530, rs530-a, x.21 modes, noload 0.2 ma all digital pins = gnd or v cc ) rs530, rs530-a, x.21 modes, full load 0.2 ma v dd = 8.73v v.28 mode, no load 1 ma v.28 mode, full load 12 ma no-cable mode 10 m a p d internal power dissipation (dce mode, rs530, rs530-a, x.21 modes, full load 300 mw (all digital pins = gnd or v cc ) v.28 mode, full load 54 mw absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 LTC1544 the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) symbol parameter conditions min typ max units logic inputs and outputs v ih logic input high voltage l 2v v il logic input low voltage l 0.8 v i in logic input current d1, d2, d3, d4 l 10 m a m0, m1, m2, dce, invert = gnd (LTC1544c) l C 100 C 50 C 30 m a m0, m1, m2, dce, invert = gnd (LTC1544i) l C 120 C 50 C 30 m a m0, m1, m2, dce, invert = v cc l 10 m a v oh output high voltage i o = C 4ma l 3 4.5 v v ol output low voltage i o = 4ma l 0.3 0.8 v i osr output short-circuit current 0v v o v cc l C50 40 50 ma i ozr three-state output current m0 = m1 = m2 = v cc , 0v v o v cc 1 m a v.11 driver v odo open circuit differential output voltage r l = 1.95k (figure 1) l 5v v odl loaded differential output voltage r l = 50 w (figure 1) 0.5v odo 0.67v odo v r l = 50 w (figure 1) l 2v d v od change in magnitude of differential r l = 50 w (figure 1) l 0.2 v output voltage v oc common mode output voltage r l = 50 w (figure 1) l 3v d v oc change in magnitude of common mode r l = 50 w (figure 1) l 0.2 v output voltage i ss short-circuit current v out = gnd 150 ma i oz output leakage current C 0.25v v o 0.25v, power off or l 1 100 m a no-cable mode or driver disabled t r , t f rise or fall time LTC1544c (figures 2, 5) l 21525 ns LTC1544i (figures 2, 5) l 21535 ns t plh input to output LTC1544c (figures 2, 5) l 20 40 65 ns LTC1544i (figures 2, 5) l 20 40 75 ns t phl input to output LTC1544c (figures 2, 5) l 20 40 65 ns LTC1544i (figures 2, 5) l 20 40 75 ns d t input to output difference, ? t plh C t phl ? LTC1544c (figures 2, 5) l 0312 ns LTC1544i (figures 2, 5) l 0317 ns t skew output to output skew (figures 2, 5) 3 ns v.11 receiver v th input threshold voltage C 7v v cm 7v l C 0.2 0.2 v d v th input hysteresis C 7v v cm 7v l 15 40 mv i in input current (a, b) C 10v v a,b 10v l 0.66 ma r in input impedance C 10v v a,b 10v l 15 30 k w t r , t f rise or fall time (figures 2, 6) 15 ns t plh input to output LTC1544c (figures 2, 6) l 50 80 ns LTC1544i (figures 2, 6) l 50 90 ns t phl input to output LTC1544c (figures 2, 6) l 50 80 ns LTC1544i (figures 2, 6) l 50 90 ns d t input to output difference, ? t plh C t phl ? LTC1544c (figures 2, 6) l 0416 ns LTC1544i (figures 2, 6) l 0421 ns electrical characteristics
4 LTC1544 note 1: absolute maximum ratings are those beyond which the safety of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified. note 3: all typicals are given for v cc = 5v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 and t a = 25 c. symbol parameter conditions min typ max units v.10 driver v o output voltage open circuit, r l = 3.9k l 4 6v v t output voltage r l = 450 w (figure 3) l 3.6 v r l = 450 w (figure 3) 0.9v o i ss short-circuit current v o = gnd 150 ma i oz output leakage current C 0.25v v o 0.25v, power off or l 0.1 100 m a no-cable mode or driver disabled t r , t f rise or fall time r l = 450 w , c l = 100pf (figures 3, 7) 2 m s t plh input to output r l = 450 w , c l = 100pf (figures 3, 7) 1 m s t phl input to output r l = 450 w , c l = 100pf (figures 3, 7) 1 m s v.10 receiver v th receiver input threshold voltage l C 0.25 0.25 v d v th receiver input hysteresis l 25 50 mv i in receiver input current C 10v v a 10v l 0.66 ma r in receiver input impedance C 10v v a 10v l 15 30 k w t r , t f rise or fall time (figures 4, 8) 15 ns t plh input to output (figures 4, 8) 55 ns t phl input to output (figures 4, 8) 109 ns d t input to output difference, ? t plh C t phl ? (figures 4, 8) 60 ns v.28 driver v o output voltage open circuit l 10 v r l = 3k (figure 3) l 5 8.5 v i ss short-circuit current v o = gnd l 150 ma i oz output leakage current C 0.25v v o 0.25v, power off or l 1 100 m a no-cable mode or driver disabled sr slew rate r l = 3k, c l = 2500pf (figures 3, 7) l 430v/ m s t plh input to output r l = 3k, c l = 2500pf (figures 3, 7) l 1.3 2.5 m s t phl input to output r l = 3k, c l = 2500pf (figures 3, 7) l 1.3 2.5 m s v.28 receiver v thl input low threshold voltage l 1.5 0.8 v v tlh input high threshold voltage l 2 1.6 v d v th receiver input hysterisis l 0 0.1 0.3 v r in receiver input impedance C 15v v a 15v l 357 k w t r , t f rise or fall time (figures 4, 8) 15 ns t plh input to output (figures 4, 8) l 60 100 ns t phl input to output (figures 4, 8) l 150 450 ns the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) electrical characteristics
5 LTC1544 v cc (pin 1): positive supply for the transceivers. 4.75v v cc 5.25v. connect a 1 m f capacitor to ground. v dd (pin 2): positive supply voltage for v.28. connect to v dd pin 3 on ltc1543 or 8v supply. connect a 1 m f capacitor to ground. d1 (pin 3): ttl level driver 1 input. d2 (pin 4): ttl level driver 2 input. d3 (pin 5): ttl level driver 3 input. r1 (pin 6): cmos level receiver 1 output. r2 (pin 7): cmos level receiver 2 output. r3 (pin 8): cmos level receiver 3 output. d4 (pin 9): ttl level driver 4 input. r4 (pin 10): cmos level receiver 4 output. m0 (pin 11): ttl level mode select input 0 with pull-up to v cc . m1 (pin 12): ttl level mode select input 1 with pull-up to v cc . m2 (pin 13): ttl level mode select input 2 with pull-up to v cc . dce/dte (pin 14): ttl level mode select input with pull-up to v cc . invert (pin 15): ttl level mode select input with pull- up to v cc . d4/r4 a (pin 16): receiver 4 inverting input and driver 4 output. r3 b (pin 17): receiver 3 noninverting input. r3 a (pin 18): receiver 3 inverting input. r2 b (pin 19): receiver 2 noninverting input. r2 a (pin 20): receiver 2 inverting input. d3/r1 b (pin 21): receiver 1 noninverting input and driver 3 noninverting output. d3/r1 a (pin 22): receiver 1 inverting input and driver 3 inverting output. d2 b (pin 23): driver 2 noninverting output. d2 a (pin 24): driver 2 inverting output. d1 b (pin 25): driver 1 noninverting output. d1 a (pin 26): driver 1 inverting output. gnd (pin 27): ground. v ee (pin 28): negative supply voltage. connect to v ee pin 26 on ltc1543 or to C 8v supply. connect a 1 m f capacitor to ground. figure 1. v.11 driver test circuit a b a r b 1544 f02 r l 100 w c l 100pf c l 100pf 15pf a b 1544 f01 v od v oc r l 50 w r l 50 w figure 2. v.11 driver/receiver ac test circuit uu u pi fu ctio s test circuits
6 LTC1544 figure 3. v.10/v.28 driver test circuit figure 4. v.10/v.28 receiver test circuit a d 1544 f04 15pf r a a d 1544 f03 r l c l LTC1544 mode name m2 m1 m0 dce/dte invert d1 d2 d3 r1 r2 r3 d4 r4 not used (default v.11) 0 0 0 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 rs530a 0 0 1 0 0 v.11 v.10 z v.11 v.10 v.11 z v.10 rs530 0 1 0 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 x.21 0 1 1 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 v.35 1 0 0 0 0 v.28 v.28 z v.28 v.28 v.28 z v.28 rs449/v.36 1 0 1 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 v.28/rs232 1 1 0 0 0 v.28 v.28 z v.28 v.28 v.28 z v.28 no cable 1 1 1 0 0 z z z zzzz z not used (default v.11) 0 0 0 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z rs530a 0 0 1 0 1 v.11 v.10 z v.11 v.10 v.11 v.10 z rs530 0 1 0 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z x.21 0 1 1 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z v.35 1 0 0 0 1 v.28 v.28 z v.28 v.28 v.28 v.28 z rs449/v.36 1 0 1 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z v.28/rs232 1 1 0 0 1 v.28 v.28 z v.28 v.28 v.28 v.28 z no cable 1 1 1 0 1 z z z zzzz z not used (default v.11) 0 0 0 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z rs530a 0 0 1 1 0 v.11 v.10 v.11 z v.10 v.11 v.10 z rs530 0 1 0 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z x.21 0 1 1 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z v.35 1 0 0 1 0 v.28 v.28 v.28 z v.28 v.28 v.28 z rs449/v.36 1 0 1 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z v.28/rs232 1 1 0 1 0 v.28 v.28 v.28 z v.28 v.28 v.28 z no cable 1 1 1 1 0 z z z zzzz z not used (default v.11) 0 0 0 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 rs530a 0 0 1 1 1 v.11 v.10 v.11 z v.10 v.11 z v.10 rs530 0 1 0 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 x.21 0 1 1 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 v.35 1 0 0 1 1 v.28 v.28 v.28 z v.28 v.28 z v.28 rs449/v.36 1 0 1 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 v.28/rs232 1 1 0 1 1 v.28 v.28 v.28 z v.28 v.28 z v.28 no cable 1 1 1 1 1 z z z zzzz z ode selectio w u test circuits
7 LTC1544 figure 7. v.10, v.28 driver propagation delays figure 6. v.11, v.35 receiver propagation delays figure 8. v.10, v.28 receiver propagation delays 3v 0v 1.5v 0v ?v 3v 1.5v 0v 3v ?v t phl t f v o ? o d a t plh t r 1544 f07 v od2 ? od2 0v 1.5v 0v 1.5v t plh v oh v ol b ?a r t phl 1544 f06 f = 1mhz : t r 10ns : t f 10ns input output v ih v il 1.3v 0.8v 1.7v 2.4v t phl v oh v ol a r t plh 1544 f08 5v 1.5v 1.5v 50% 10% 90% t plh t r 0v v o v o ? o d b ?a a b t phl t skew t skew 1544 f05 1/2 v o f = 1mhz : t r 10ns : t f 10ns v diff = v(a) ?v(b) 50% 10% 90% t f figure 5. v.11, v.35 driver propagation delays switchi g ti e wavefor s uw w
8 LTC1544 overview the ltc1543/LTC1544 form the core of a complete soft- ware-selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 or x.21 protocols. cable termination may be implemented using the ltc1344a software-selectable cable termination chip or by using existing discrete designs. a complete dce-to-dte interface operating in eia530 mode is shown in figure 9. the ltc1543 of each port is used to generate the clock and data signals. the LTC1544 is used to generate the control signals along with ll (local loop-back).the ltc1344a cable termination chip is used only for the clock and data signals because they must support v.35 cable termination. the control signals do not need any external resistors. figure 9. complete multiprotocol interface in eia530 mode ltc1543 dce dte ltc1543 ltc1344a ltc1344a 1544 f09 d3 d3 r1 103 w 103 w 103 w r3 LTC1544 d4 r1 r2 r3 ll txc rxc rxd txd scte txc rxc rxd serial controller d2 103 w scte r2 d1 103 w txd r3 r1 d2 d1 LTC1544 txd scte txc rxc rxd rts dtr dcd dsr cts ll rts dtr dcd dsr cts rts dtr dcd dsr cts ll serial controller r2 r4 r4 d3 d2 d1 r2 r1 r3 d2 d1 d4 d3 applicatio n s i n for m atio n wu u u
9 LTC1544 mode selection the interface protocol is selected using the mode select pins m0, m1 and m2 (see the mode selection table). for example, if the port is configured as a v.35 interface, the mode selection pins should be m2 = 1, m1 = 0, m0 = 0. for the control signals, the drivers and receivers will operate in v.28 (rs232) electrical mode. for the clock and data signals, the drivers and receivers will operate in v.35 electrical mode. the dce/dte pin will configure the port for dce mode when high, and dte when low. the interface protocol may be selected simply by plug- ging the appropriate interface cable into the connector. the mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in figure 10. the internal pull-up current sources will ensure a binary 1 when a pin is left unconnected and that the ltc1543/ LTC1544 and the ltc1344a enter the no-cable mode when the cable is removed. in the no-cable mode the ltc1543/LTC1544 supply current drops to less than 200 m a and all ltc1543/LTC1544 driver outputs and ltc1344a resistive terminations are forced into a high impedance state. the mode selection may also be accomplished by using jumpers to connect the mode pins to ground or v cc . nc nc cable 1544 f10 11 12 13 14 ltc1543 LTC1544 connector 14 13 12 11 22 21 m2 m1 ltc1344a latch m0 (data) 23 24 1 (data) m0 m1 m2 dce/dte dce/dte m2 m1 m0 (data) dce/ dte figure 10: single port dce v.35 mode selection in the cable applicatio n s i n for m atio n wu u u
10 LTC1544 cable termination traditional implementations have included switching resistors with expensive relays, or requiring the user to change termination modules every time the interface standard has changed. custom cables have been used with the termination in the cable head or separate termina- tions are built on the board and a custom cable routes the signals to the appropriate termination. switching the terminations with fets is difficult because the fets must remain off even though the signal voltage is beyond the supply voltage for the fet drivers or the power is off. using the ltc1344a along with the ltc1543/LTC1544 solves the cable termination switching problem. via soft- ware control, the ltc1344a provides termination for the v.10 (rs423), v.11 (rs422), v.28 (rs232) and v.35 electrical protocols. v.10 (rs423) interface a typical v.10 unbalanced interface is shown in figure 11. a v.10 single-ended generator output a with ground c is connected to a differential receiver with inputs a ' con- nected to a, and input c ' connected to the signal return ground c. usually, no cable termination is required for v.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in figure 12. the v.10 receiver configuration in the LTC1544 is shown in figure 13. in v.10 mode switch s3 inside the LTC1544 is turned off.the noninverting input is disconnected inside the LTC1544 receiver and connected to ground. the cable termination is then the 30k input impedance to ground of the LTC1544 v.10 receiver. i z v z 10v ?.25ma 3.25ma ?v 3v 10v 1544 f12 figure 12. v.10 receiver input impedance figure 11. typical v.10 interface figure 13. v.10 receiver configuration aa ' cc ' generator balanced interconnecting cable load cable termination receiver 1544 f11 r5 20k LTC1544 receiver 1544 f13 a b a ' b ' c ' r8 6k s3 r6 10k r7 10k gnd r4 20k applicatio n s i n for m atio n wu u u
11 LTC1544 v.11 (rs422) interface a typical v.11 balanced interface is shown in figure 14. a v.11 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.11 interface has a differential termination at the receiver end that has a minimum value of 100 w . the termination resistor is optional in the v.11 specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. the receiver inputs must also be compliant with the imped- ance curve shown in figure 12. in v.11 mode, all switches are off except s1 inside the ltc1344a which connects a 103 w differential termina- tion impedance to the cable as shown in figure 15. r3 124 w r5 20k ltc1344a ltc1543 LTC1544 receiver 1544 f15 a b a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 figure 15. v.11 receiver configuration aa ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 100 w min 1544 f14 v.28 (rs232) interface a typical v.28 unbalanced interface is shown in figure 16. a v.28 single-ended generator output a with ground c is connected to a single-ended receiver with input a ' con- nected to a, ground c ' connected via the signal return ground c. in v.28 mode all switches are off except s3 inside the ltc1543/LTC1544 which connects a 6k (r8) impedance to ground in parallel with 20k (r5) plus 10k (r6) for a combined impedance of 5k as shown in figure 17. the noninverting input is disconnected inside the ltc1543/ LTC1544 receiver and connected to a ttl level reference voltage for a 1.4v receiver trip point. aa ' cc ' generator balanced interconnecting cable load cable termination receiver 1544 f16 figure 14. typical v.11 interface r3 124 w r5 20k ltc1344a ltc1543 LTC1544 receiver 1544 f17 a b a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 figure 17. v.28 receiver configuration figure 16. typical v.28 interface applicatio n s i n for m atio n wu u u
12 LTC1544 a a ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 1544 f18 50 w 125 w 50 w 50 w 125 w 50 w figure 18. typical v.35 interface r3 124 w r5 20k ltc1344a ltc1543 receiver 1544 f19 a b a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 figure 19. v.35 receiver configuration v.35 interface a typical v.35 balanced interface is shown in figure 18. a v.35 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.35 interface requires a t or delta network termination at the receiver end and the generator end. the receiver differential impedance measured at the connector must be 100 w 10 w , and the impedance between shorted termi- nals (a ' and b ' ) and ground c ' must be 150 w 15 w . in v.35 mode, both switches s1 and s2 inside the ltc1344a are on, connecting the t network impedance as shown in figure 19. the switch in the ltc1543 is off. the 30k input impedance of the receiver is placed in parallel with the t network termination, but does not affect the overall input impedance significantly. applicatio n s i n for m atio n wu u u
13 LTC1544 charge pump the ltc1543 uses an internal capacitive charge pump to generate v dd and v ee as shown in figure 21. a voltage doubler generates about 8v on v dd and a voltage inverter generates about C 7.5v for v ee . four 1 m f surface mounted tantalum or ceramic capacitors are required for c1, c2, c3 and c4. the v ee capacitor c5 should be a minimum of 3.3 m f. all capacitors are 16v and should be placed as close as possible to the ltc1543 to reduce emi. the generator differential impedance must be 50 w to 150 w and the impedance between shorted terminals (a and b) and ground c must be 150 w 15 w . for the generator termination, switches s1 and s2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in figure 20. figure 20. v.35 driver using the ltc1344a v.35 driver a b c 51.5 w s2 on s1 on 1544 f20 51.5 w ltc1344a 124 w c1 100pf 28 27 26 25 1544 f21 3 2 1 4 c3 1 m f c4 1 m f 5v c1 1 m f c2 1 m f c5 3.3 m f ltc1543 v dd c1 + c1 v cc c2 + c2 v ee gnd + figure 21. charge pump any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground, causing a high frequency common mode spike on the a and b terminals. the common mode spike can cause emi problems that are reduced by capacitor c1 which shunts much of the com- mon mode energy to ground rather than down the cable. no-cable mode the no-cable mode (m0 = m1 = m2 = 1) is intended for the case when the cable is disconnected from the connector. the charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 200 m a. receiver fail-safe all ltc1543/LTC1544 receivers feature fail-safe opera- tion in all modes. if the receiver inputs are left floating or shorted together by a termination resistor, the receiver output will always be forced to a logic high. dte vs dce operation the dce/dte pin acts as an enable for driver 3/receiver 1 in the ltc1543, and driver 3/receiver 1 and driver 4/ receiver 4 in the LTC1544. the invert pin in the LTC1544 allows the driver 4/receiver 4 enable to be high or low true polarity. applicatio n s i n for m atio n wu u u
14 LTC1544 the ltc1543/LTC1544 can be configured for either dte or dce operation in one of two ways: a dedicated dte or dce port with a connector of appropriate gender or a port with one connector that can be configured for dte or dce operation by rerouting the signals to the ltc1543/LTC1544 using a dedicated dte cable or dedicated dce cable. a dedicated dte port using a db-25 male connector is shown in figure 22. the interface mode is selected by logic outputs from the controller or from jumpers to either v cc or gnd on the mode select pins. a dedicated dce port using a db-25 female connector is shown in figure 23. a port with one db-25 connector, but can be configured for either dte or dce operation is shown in figure 24. the configuration requires separate cables for proper signal routing in dte or dce operation. for example, in dte mode, the txd signal is routed to pins 2 and 14 via driver 1 in the ltc1543. in dce mode, driver 1 now routes the rxd signal to pins 2 and 14. multiprotocol interface with rl, ll, tm and a db-25 connector if the rl, ll and tm signals are implemented, there are not enough drivers and receivers available in the ltc1543/ LTC1544. in figure 25, the required control signals are handled by the LTC1544 but the clock/data signals use the ltc1343. the ltc1343 has an additional single-ended driver/receiver pair that can handle two more optional control signals such as tm and ll. cable-selectable multiprotocol interface a cable-selectable multiprotocol dte/dce interface is shown in figure 26. the select lines m0, m1 and dce/dte are brought out to the connector. the mode is selected by the cable by wiring m0 (connector pin 18) and m1 (con- nector pin 21) and dce/dte (connector pin 25) to ground (connector pin 7) or letting them float. if m0, m1 or dce/ dte is floating, internal pull-up current sources will pull the signals to v cc . the select bit m2 is hard wired to v cc . when the cable is pulled out, the interface will go into the no-cable mode. compliance testing a european standard en 45001 test report is available for the ltc1543/LTC1544/ltc1344a chipset. a copy of the test report is available from ltc or tuv telecom services inc. (formerly detecon inc.) the title of the report is: test report no. net2/102201/97. the address of tuv telecom services inc. is: tuv telecom services inc. type approval division 1775 old highway 8, ste 107 st. paul, mn 55112 usa tel. +1 (612) 639-0775 fax. +1 (612) 639-0873 applicatio n s i n for m atio n wu u u
15 LTC1544 figure 22. controller-selectable multiprotocol dte port with db-25 connector d2 d1 LTC1544 rts dtr dsr dcd cts d3 r2 r1 r4 r3 d2 ltc1543 ll txd scte txc rxc rxd m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 2 21 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 18 7 16 1544 f22 d3 r2 r1 r3 d1 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f txd a (103) txd b scte a (113) scte b rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b ll a (141) sg shield db-25 male connector txc a (114) txc b dcd a (109) dcd b dsr a (107) dsr b d4 16 10 9 7 6 4 3 8 11 12 13 5 2 15 18 17 19 20 22 ltc1344a latch c6 100pf c7 100pf c8 100pf v cc v cc 5v 23 24 14 1 dce/dte m2 m1 m0 charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 10 9 invert 15 16 17 18 19 20 21 22 23 24 25 nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 v ee m0 m1 m2 dce/dte m2 m1 m0 11 12 13 14 c12 1 f c13 1 f c11 1 f c10 1 f c9 1 f typical applicatio s u
16 LTC1544 figure 23. controller-selectable dce port with db-25 connector d2 d1 LTC1544 cts dsr dtr dcd rts d3 r2 r1 r4 r3 d2 ltc1543 ll rxd rxc txc scte txd m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 3 16 17 9 15 12 24 11 2 1 5 13 6 8 22 10 20 23 4 19 18 7 14 1544 f23 d3 r2 r1 r3 d1 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f rxd a (104) rxd b rxc a (115) rxc b scte a (113) scte b txd a (103) txd b cts a (106) cts b dsr a (107) dsr b rts a (105) rts b ll a (141) sgnd (102) shield (101) db-25 female connector txc a (114) txc b dcd a (109) dcd b dtr a (108) dtr b d4 16 10 9 7 6 4 3 8 11 12 13 5 2 15 18 17 19 20 22 ltc1344a c6 100pf c7 100pf c8 100pf v cc v cc v cc 5v 23 24 14 1 dce/dte m2 m1 m0 charge pump + 28 3 1 2 4 5 6 7 8 9 10 nc 11 12 13 14 1 2 3 4 5 6 7 8 10 9 invert 15 16 17 18 19 20 21 22 23 24 25 nc nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 v ee m0 m1 m2 dce/dte m2 m1 m0 11 12 13 14 21 latch c12 1 f c13 1 f c11 1 f c10 1 f c9 1 f typical applicatio s u
17 LTC1544 figure 24. controller-selectable multiprotocol dte/dce port with db-25 connector d2 d1 LTC1544 d3 r2 r1 r4 r3 d2 ltc1543 dte_txd/dce_rxd dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ll/dce_ll dte_scte/dce_rxc m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 18 7 16 1544 f24 d3 r2 r1 r3 d1 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f txd a txd b scte a scte b rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b ll a sg shield db-25 connector txc a txc b scte a scte b txd a txd b txc a txc b dcd a dcd b dsr a dsr b rts a rts b ll a dcd a dcd b dtr a dtr b d4 16 10 9 7 6 4 3 8 11 12 13 5 2 15 18 17 19 20 22 ltc1344a c6 100pf c7 100pf c8 100pf v cc v cc 5v 23 24 14 1 dce/dte m2 m1 m0 charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 10 9 invert 15 16 17 18 19 20 21 22 23 24 25 nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 v ee m0 m1 m2 dce/dte dce/dte m2 m1 m0 11 12 13 14 dte dce 21 latch c12 1 f c13 1 f c11 1 f c10 1 f c9 1 f typical applicatio s u
18 LTC1544 figure 25. controller-selectable multiprotocol dte/dce port with rl, ll, tm and db-25 connector d2 d1 LTC1544 d3 r2 r1 r4 r3 d2 ltc1343 dte_ll/dce_tm dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_tm/dce_ll dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_rl/dce_rl dte_txd/dce_rxd dte_scte/dce_rxc ctrl latch invert 423set gnd dce m2 m1 m0 ec v cc v dd v cc v ee gnd 2 18 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 21 7 16 25 1544 f25 d3 d4 r2 r3 r4 d1 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f ll a txd a txd b scte a scte b tm a rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b rl a sg shield db-25 connector txc a txc b scte a scte b txd a txd b txc a txc b dcd a dcd b dsr a dsr b rts a rts b rl a dcd a dcd b dtr a dtr b d4 16 10 9 7 6 4 3 8 11 12 13 5 2 15 18 17 19 20 22 ltc1344a c6 100pf c7 100pf c8 100pf v cc v cc 5v 23 24 14 1 dce/dte m2 m1 m0 charge pump + 44 3 1 2 4 5 8 6 7 9 10 12 13 14 15 16 20 22 11 1 r1 100k 2 3 4 5 6 7 8 10 9 invert 15 16 17 18 19 20 21 22 23 24 25 nc 43 42 41 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 24 26 27 28 v ee m0 m1 m2 dce/dte dce/dte m2 m1 m0 11 12 13 14 dte dce r1 25 40 23 v cc lb lb tm a ll a 21 latch c12 1 f c13 1 f c11 1 f c10 1 f c9 1 f typical applicatio s u
19 LTC1544 d2 d1 LTC1544 d3 r2 r1 r4 r3 d2 ltc1543 dte_txd/dce_rxd dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_scte/dce_rxc m0 m1 m2 dce/dte v cc v dd nc nc v cc v ee gnd 2 v cc 14 24 11 15 12 17 9 3 1 25 21 18 4 19 20 8 23 10 6 22 5 13 7 16 1544 f26 d3 r2 r1 r3 d1 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f txd a txd b scte a scte b rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b sg shield dce/dte m1 m0 db-25 connector txc a txc b scte a scte b txd a txd b txc a txc b dcd a dcd b dsr a dsr b rts a rts b dcd a dcd b dtr a dtr b d4 16 10 9 7 6 4 3 8 11 12 13 5 2 15 18 17 19 20 22 ltc1344a c6 100pf c7 100pf c8 100pf v cc v cc 5v 23 24 14 1 dce/dte m2 m1 m0 charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 invert 15 17 16 18 19 20 21 22 23 24 25 nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 v ee m0 m1 m2 dce/dte 11 12 13 14 dte dce mode pin 18 pin 21 v.35 pin 7 pin 7 rs449, v.36 nc pin 7 rs232 pin 7 nc cable wiring for mode selection mode pin 25 dte pin 7 dce nc cable wiring for dte/dce selection 21 latch c12 1 f c13 1 f c11 1 f c10 1 f c9 1 f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. figure 26. cable-selectable multiprotocol dte/dce port with db-25 connector typical applicatio s u
20 LTC1544 1544fa lt/tp 0100 2k rev a ? printed in usa ? linear technology corporation 1998 related parts part number description comments ltc1321 dual rs232/rs485 transceiver two rs232 driver/receiver pairs or two rs485 driver/receiver pairs ltc1334 single 5v rs232/rs485 multiprotocol transceiver two rs232 driver/receiver or four rs232 driver/receiver pairs ltc1343 software-selectable multiprotocol transceiver 4-driver/4-receiver for data and clock signals ltc1344a software-selectable cable terminator perfect for terminating the ltc1543 ltc1345 single supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1346a dual supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1543 software-selectable multiprotocol transceiver companion to LTC1544 for data and clock signals ltc1546 multiprotocol transceiver with termination companion to LTC1544 for data and clock signals dimensions in inches (millimeters) unless otherwise noted. g28 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 13 10.07 ?10.33* (0.397 ?0.407) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com u package descriptio

▲Up To Search▲

Price & Availability of LTC1544

	To Download LTC1544 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .